Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs.

Tsung-Yi Wu Tzi-Wei Kao How-Rern Lin Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs. 2581-2589 2010 93-A IEICE Transactions 12 http://search.ieice.org/bin/summary.php?id=e93-a_12_2581 db/journals/ieicet/ieicet93a.html#WuKL10