Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit.

Masayuki Uno Shoji Kawahito Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit. 702-709 2006 89-C IEICE Transactions 6 http://dx.doi.org/10.1093/ietele/e89-c.6.702 db/journals/ieicet/ieicet89c.html#UnoK06