<?xml version="1.0"?>
<dblp>
<article key="journals/ieicet/TsunodaSTNT05" mdate="2008-01-25">
<author>Kouji Tsunoda</author>
<author>Akira Sato</author>
<author>Hiroko Tashiro</author>
<author>Toshiro Nakanishi</author>
<author>Hitoshi Tanaka</author>
<title>Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications.</title>
<pages>608-613</pages>
<year>2005</year>
<volume>88-C</volume>
<journal>IEICE Transactions</journal>
<number>4</number>
<ee>http://dx.doi.org/10.1093/ietele/e88-c.4.608</ee>
<url>db/journals/ieicet/ieicet88c.html#TsunodaSTNT05</url>
</article>
</dblp>
