0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier.

Toshikazu Suzuki Yoshinobu Yamagami Ichiro Hatanaka Akinori Shibayama Hironori Akamatsu Hiroyuki Yamauchi 0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. 630-638 2005 88-C IEICE Transactions 4 http://dx.doi.org/10.1093/ietele/e88-c.4.630 db/journals/ieicet/ieicet88c.html#SuzukiYHSAY05