BibTeX record journals/ieicet/SuzukiYHSAY05

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@article{DBLP:journals/ieicet/SuzukiYHSAY05,
  author       = {Toshikazu Suzuki and
                  Yoshinobu Yamagami and
                  Ichiro Hatanaka and
                  Akinori Shibayama and
                  Hironori Akamatsu and
                  Hiroyuki Yamauchi},
  title        = {0.3-1.5 {V} Embedded {SRAM} Core with Write-Replica Circuit Using
                  Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier},
  journal      = {{IEICE} Trans. Electron.},
  volume       = {88-C},
  number       = {4},
  pages        = {630--638},
  year         = {2005},
  url          = {https://doi.org/10.1093/ietele/e88-c.4.630},
  doi          = {10.1093/IETELE/E88-C.4.630},
  timestamp    = {Mon, 05 Feb 2024 20:20:43 +0100},
  biburl       = {https://dblp.org/rec/journals/ieicet/SuzukiYHSAY05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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