A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond.

Yasuhiro Morita Hidehiro Fujiwara Hiroki Noguchi Kentaro Kawakami Junichi Miyakoshi Shinji Mikami Koji Nii Hiroshi Kawaguchi Masahiko Yoshimoto A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. 3634-3641 2006 89-A IEICE Transactions 12 http://dx.doi.org/10.1093/ietfec/e89-a.12.3634 db/journals/ieicet/ieicet89a.html#MoritaFNKMMNKY06