Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm.

Shoichi Masui Kenji Mukaida Masahiko Takenaka Naoya Torii Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm. 576-581 2005 88-C IEICE Transactions 4 http://dx.doi.org/10.1093/ietele/e88-c.4.576 db/journals/ieicet/ieicet88c.html#MasuiMTT05