Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits.

Zheng Liu Masanori Furuta Shoji Kawahito Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits. 710-716 2006 89-C IEICE Transactions 6 http://dx.doi.org/10.1093/ietele/e89-c.6.710 db/journals/ieicet/ieicet89c.html#LiuFK06