BibTeX record journals/ieicet/JianCCG12

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@article{DBLP:journals/ieicet/JianCCG12,
  author       = {Guo{-}An Jian and
                  Cheng{-}An Chien and
                  Peng{-}Sheng Chen and
                  Jiun{-}In Guo},
  title        = {A Verification-Aware Design Methodology for Thread Pipelining Parallelization},
  journal      = {{IEICE} Trans. Inf. Syst.},
  volume       = {95-D},
  number       = {10},
  pages        = {2505--2513},
  year         = {2012},
  url          = {https://doi.org/10.1587/transinf.E95.D.2505},
  doi          = {10.1587/TRANSINF.E95.D.2505},
  timestamp    = {Sat, 11 Apr 2020 15:26:04 +0200},
  biburl       = {https://dblp.org/rec/journals/ieicet/JianCCG12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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