Timed verification of the generic architecture of a memory circuit using parametric timed automata.

Remy Chevallier Emmanuelle Encrenaz-Tiphène Laurent Fribourg Weiwen Xu Timed verification of the generic architecture of a memory circuit using parametric timed automata. 59-81 2009 34 Formal Methods in System Design 1 http://dx.doi.org/10.1007/s10703-008-0061-x db/journals/fmsd/fmsd34.html#ChevallierEFX09