Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.

Yongsoon Lee Younhee Choi Moon Ho Lee Seok-Bum Ko Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector. 2009 2009 EURASIP J. Emb. Sys. http://dx.doi.org/10.1155/2009/258921 db/journals/ejes/ejes2009.html#LeeCLK09