Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits.

Ashish Pancholy Janusz Rajski Larry J. McNaughton Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. 72-83 1992 9 IEEE Design & Test of Computers 1 http://doi.ieeecomputersociety.org/10.1109/54.124519 db/journals/dt/dt9.html#PancholyRM92