Leakage Minimization Technique for Nanoscale CMOS VLSI.

Kyung Ki Kim Yong-Bin Kim Minsu Choi Nohpill Park Leakage Minimization Technique for Nanoscale CMOS VLSI. 322-330 2007 24 IEEE Design & Test of Computers 4 http://doi.ieeecomputersociety.org/10.1109/MDT.2007.141 db/journals/dt/dt24.html#KimKCP07