BibTeX record journals/corr/abs-1709-07241

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@article{DBLP:journals/corr/abs-1709-07241,
  author       = {Suchandra Banerjee and
                  Anand Ratna and
                  Suchismita Roy},
  title        = {Satisfiability Modulo Theory based Methodology for Floorplanning in
                  {VLSI} Circuits},
  journal      = {CoRR},
  volume       = {abs/1709.07241},
  year         = {2017},
  url          = {http://arxiv.org/abs/1709.07241},
  eprinttype    = {arXiv},
  eprint       = {1709.07241},
  timestamp    = {Mon, 13 Aug 2018 16:46:21 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-1709-07241.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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