Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture

Alexandre M. Amory Marcelo Lubaszewski Fernando Gehm Moraes Edson I. Moreno Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture http://arxiv.org/abs/0710.4795 2007 CoRR abs/0710.4795 db/journals/corr/corr0710.html#abs-0710-4795 informal publication