Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

Matthias Beck Olivier Barondeau Martin Kaibel Frank Poehl Xijiang Lin Ron Press Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality http://arxiv.org/abs/0710.4763 2007 CoRR abs/0710.4763 db/journals/corr/corr0710.html#abs-0710-4763 informal publication