BibTeX record journals/corr/VeselyMHR15

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@article{DBLP:journals/corr/VeselyMHR15,
  author       = {Vladim{\'{\i}}r Vesel{\'{y}} and
                  Marcel Marek and
                  Tomas Hykel and
                  Ondrej Rysav{\'{y}}},
  title        = {Skip This Paper - RINASim: Your Recursive InterNetwork Architecture
                  Simulator},
  journal      = {CoRR},
  volume       = {abs/1509.03550},
  year         = {2015},
  url          = {http://arxiv.org/abs/1509.03550},
  eprinttype    = {arXiv},
  eprint       = {1509.03550},
  timestamp    = {Mon, 13 Aug 2018 16:49:03 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/VeselyMHR15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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