Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses.

Chuanjun Zhang Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses. 2-5 2006 5 Computer Architecture Letters 1 http://dx.doi.org/10.1109/L-CA.2006.3 db/journals/cal/cal5.html#Zhang06