Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations.

Yong Ki Lee Herwin Chan Ingrid Verbauwhede Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations. 102-114 2007 conf/wisa/2007 WISA http://dx.doi.org/10.1007/978-3-540-77535-5_8 db/conf/wisa/wisa2007.html#LeeCV07