BibTeX record conf/vts/WangLPHW05

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@inproceedings{DBLP:conf/vts/WangLPHW05,
  author       = {Chun{-}Chieh Wang and
                  Jing{-}Jia Liou and
                  Yen{-}Lin Peng and
                  Chih{-}Tsun Huang and
                  Cheng{-}Wen Wu},
  title        = {A {BIST} Scheme for {FPGA} Interconnect Delay Faults},
  booktitle    = {23rd {IEEE} {VLSI} Test Symposium {(VTS} 2005), 1-5 May 2005, Palm
                  Springs, CA, {USA}},
  pages        = {201--206},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/VTS.2005.5},
  doi          = {10.1109/VTS.2005.5},
  timestamp    = {Sat, 30 Sep 2023 09:58:40 +0200},
  biburl       = {https://dblp.org/rec/conf/vts/WangLPHW05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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