BibTeX record: conf/vts/WangLPHW05

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@inproceedings{DBLP:conf/vts/WangLPHW05,
  author    = {Chun{-}Chieh Wang and
               Jing{-}Jia Liou and
               Yen{-}Lin Peng and
               Chih{-}Tsun Huang and
               Cheng{-}Wen Wu},
  title     = {A {BIST} Scheme for {FPGA} Interconnect Delay Faults},
  booktitle = {23rd {IEEE} {VLSI} Test Symposium {(VTS} 2005), 1-5 May 2005, Palm
               Springs, CA, {USA}},
  year      = {2005},
  pages     = {201--206},
  crossref  = {DBLP:conf/vts/2005},
  url       = {http://doi.ieeecomputersociety.org/10.1109/VTS.2005.5},
  doi       = {10.1109/VTS.2005.5},
  timestamp = {Sat, 20 Sep 2014 08:14:43 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/vts/WangLPHW05},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/vts/2005,
  title     = {23rd {IEEE} {VLSI} Test Symposium {(VTS} 2005), 1-5 May 2005, Palm
               Springs, CA, {USA}},
  year      = {2005},
  publisher = {{IEEE} Computer Society},
  isbn      = {0-7695-2314-5},
  timestamp = {Sat, 20 Sep 2014 08:14:43 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/vts/2005},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}