Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.

Nandu Tendolkar Rajesh Raina Rick Woltenberg Xijiang Lin Bruce Swanson Greg Aldrich Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. 3-8 2002 conf/vts/2002 VTS http://csdl.computer.org/comp/proceedings/vts/2002/1570/00/15700003abs.htm db/conf/vts/vts2002.html#TendolkarRWLSA02