BibTeX record conf/vts/RadeckaZ00

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@inproceedings{DBLP:conf/vts/RadeckaZ00,
  author       = {Katarzyna Radecka and
                  Zeljko Zilic},
  title        = {Using Arithmetic Transform for Verification of Datapath Circuits via
                  Error Modeling},
  booktitle    = {18th {IEEE} {VLSI} Test Symposium {(VTS} 2000), 30 April - 4 May 2000,
                  Montreal, Canada},
  pages        = {271--280},
  publisher    = {{IEEE} Computer Society},
  year         = {2000},
  url          = {https://doi.org/10.1109/VTEST.2000.843855},
  doi          = {10.1109/VTEST.2000.843855},
  timestamp    = {Fri, 24 Mar 2023 00:04:05 +0100},
  biburl       = {https://dblp.org/rec/conf/vts/RadeckaZ00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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