BibTeX record conf/vts/ChoS11

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@inproceedings{DBLP:conf/vts/ChoS11,
  author       = {Kyoung Youn Cho and
                  Rajagopalan Srinivasan},
  title        = {A scan cell architecture for inter-clock at-speed delay testing},
  booktitle    = {29th {IEEE} {VLSI} Test Symposium, {VTS} 2011, May 1-5, 2011, Dana
                  Point, California, {USA}},
  pages        = {213--218},
  publisher    = {{IEEE} Computer Society},
  year         = {2011},
  url          = {https://doi.org/10.1109/VTS.2011.5783723},
  doi          = {10.1109/VTS.2011.5783723},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/vts/ChoS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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