A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder.

Wenjun Wang Xiaoguang Wu Xiaoxuan Zhu Guixia Kang Xiaofeng Tao A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder. 767-771 2008 VTC Spring http://dx.doi.org/10.1109/VETECS.2008.168 conf/vtc/2008s db/conf/vtc/vtc2008s.html#WangWZKT08