BibTeX record conf/vlsit/WangYXBLBJZTGSZ23

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@inproceedings{DBLP:conf/vlsit/WangYXBLBJZTGSZ23,
  author       = {Song Wang and
                  Bing Yu and
                  Wenwu Xiao and
                  Fujun Bai and
                  Xiaodong Long and
                  Liang Bai and
                  Xuerong Jia and
                  Fengguo Zuo and
                  Jie Tan and
                  Yixin Guo and
                  Peng Sun and
                  Jun Zhou and
                  Qiong Zhan and
                  Sheng Hu and
                  Yu Zhou and
                  Yi Kang and
                  Qiwei Ren and
                  Xiping Jiang},
  title        = {A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded {DRAM} with Multilayer
                  Arrays by Fine Pitch Hybrid Bonding and Mini-TSV},
  booktitle    = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
                  and Circuits), Kyoto, Japan, June 11-16, 2023},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185427},
  doi          = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185427},
  timestamp    = {Tue, 07 May 2024 20:11:30 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsit/WangYXBLBJZTGSZ23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}