BibTeX record conf/vlsit/KumarST0H0DM22

• > Home > conf/vlsit/KumarST0H0DM22

@inproceedings{DBLP:conf/vlsit/KumarST0H0DM22,
  author       = {Raghavan Kumar and
                  Vikram B. Suresh and
                  Sachin Taneja and
                  Mark A. Anders and
                  Steven Hsu and
                  Amit Agarwal and
                  Vivek De and
                  Sanu Mathew},
  title        = {A 7Gbps SCA-Resistant Multiplicative-Masked {AES} Engine in Intel
                  4 {CMOS}},
  booktitle    = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
                  and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
  pages        = {138--139},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830470},
  doi          = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830470},
  timestamp    = {Thu, 04 Aug 2022 11:27:04 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsit/KumarST0H0DM22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}