BibTeX record conf/vlsit/JiangLHY22

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@inproceedings{DBLP:conf/vlsit/JiangLHY22,
  author       = {Hongwu Jiang and
                  Wantong Li and
                  Shanshi Huang and
                  Shimeng Yu},
  title        = {A 40nm Analog-Input ADC-Free Compute-in-Memory {RRAM} Macro with Pulse-Width
                  Modulation between Sub-arrays},
  booktitle    = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
                  and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
  pages        = {266--267},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830211},
  doi          = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830211},
  timestamp    = {Tue, 21 Mar 2023 21:02:44 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsit/JiangLHY22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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