BibTeX
@inproceedings{DBLP:conf/vlsid/YanS05,
author = {Haihua Yan and
Adit D. Singh},
title = {A Delay Test to Differentiate Resistive Interconnect Faults
from Weak Transistor Defects},
booktitle = {VLSI Design},
year = {2005},
pages = {47-52},
ee = {http://csdl.computer.org/comp/proceedings/vlsid/2005/2264/00/22640047abs.htm},
crossref = {DBLP:conf/vlsid/2005},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
@proceedings{DBLP:conf/vlsid/2005,
title = {18th International Conference on VLSI Design (VLSI Design
2005), with the 4th International Conference on Embedded
Systems Design, 3-7 January 2005, Kolkata, India},
booktitle = {VLSI Design},
publisher = {IEEE Computer Society},
year = {2005},
isbn = {0-7695-2264-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2005-02-07 by Michael Ley (ley@uni-trier.de)