BibTeX record conf/vlsid/YanC07

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@inproceedings{DBLP:conf/vlsid/YanC07,
  author       = {Jin{-}Tai Yan and
                  Bo{-}Yi Chiang},
  title        = {Timing-Constrained Yield-Driven Wiring Reconstruction for Critical
                  Area Minimization},
  booktitle    = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
                  Sixth International Conference on Embedded Systems {(ICES} 2007),
                  6-10 January 2007, Bangalore, India},
  pages        = {899--906},
  publisher    = {{IEEE} Computer Society},
  year         = {2007},
  url          = {https://doi.org/10.1109/VLSID.2007.158},
  doi          = {10.1109/VLSID.2007.158},
  timestamp    = {Fri, 24 Mar 2023 00:04:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/YanC07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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