<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/vlsid/WangXRV07" mdate="2007-05-10">
<author>Feng Wang 0004</author>
<author>Yuan Xie</author>
<author>R. Rajaraman</author>
<author>Balaji Vaidyanathan</author>
<title>Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model.</title>
<pages>165-170</pages>
<year>2007</year>
<crossref>conf/vlsid/2007</crossref>
<booktitle>VLSI Design</booktitle>
<ee>http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.145</ee>
<url>db/conf/vlsid/vlsid2007.html#WangXRV07</url>
</inproceedings>
</dblp>
