BibTeX record conf/vlsid/VermaD24

download as .bib file

@inproceedings{DBLP:conf/vlsid/VermaD24,
  author       = {Anshul Verma and
                  Bishnu Prasad Das},
  title        = {A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100
                  fs {RMS} Jitter and jitter},
  booktitle    = {37th International Conference on {VLSI} Design and 23rd International
                  Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
                  6-10, 2024},
  pages        = {156--161},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/VLSID60093.2024.00032},
  doi          = {10.1109/VLSID60093.2024.00032},
  timestamp    = {Tue, 07 May 2024 20:10:04 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsid/VermaD24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.