<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/vlsid/UsamiSHMTNSANIKN09" mdate="2009-04-21">
<author>Kimiyoshi Usami</author>
<author>Toshiaki Shirai</author>
<author>Tasunori Hashida</author>
<author>Hiroki Masuda</author>
<author>Seidai Takeda</author>
<author>Mitsutaka Nakata</author>
<author>Naomi Seki</author>
<author>Hideharu Amano</author>
<author>Mitaro Namiki</author>
<author>Masashi Imai</author>
<author>Masaaki Kondo</author>
<author>Hiroshi Nakamura</author>
<title>Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.</title>
<pages>381-386</pages>
<year>2009</year>
<booktitle>VLSI Design</booktitle>
<ee>http://dx.doi.org/10.1109/VLSI.Design.2009.63</ee>
<crossref>conf/vlsid/2009</crossref>
<url>db/conf/vlsid/vlsid2009.html#UsamiSHMTNSANIKN09</url>
</inproceedings>
</dblp>
