Jayashree Sridharan Tom Chen Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. 323-328 2006 conf/vlsid/2006 VLSI Design http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.92 db/conf/vlsid/vlsid2006.html#SridharanC06