<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/vlsid/SinhaRB08" mdate="2008-04-03">
<author>Roopak Sinha</author>
<author>Partha S. Roop</author>
<author>Samik Basu</author>
<title>A Module Checking Based Converter Synthesis Approach for SoCs.</title>
<pages>492-501</pages>
<year>2008</year>
<booktitle>VLSI Design</booktitle>
<ee>http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.109</ee>
<crossref>conf/vlsid/2008</crossref>
<url>db/conf/vlsid/vlsid2008.html#SinhaRB08</url>
</inproceedings>
</dblp>
