BibTeX
@inproceedings{DBLP:conf/vlsid/SinhaRB08,
author = {Roopak Sinha and
Partha S. Roop and
Samik Basu},
title = {A Module Checking Based Converter Synthesis Approach for
SoCs},
booktitle = {VLSI Design},
year = {2008},
pages = {492-501},
ee = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.109},
crossref = {DBLP:conf/vlsid/2008},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
@proceedings{DBLP:conf/vlsid/2008,
title = {21st International Conference on VLSI Design (VLSI Design
2008), 4-8 January 2008, Hyderabad, India},
booktitle = {VLSI Design},
publisher = {IEEE Computer Society},
year = {2008},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2008-04-03 by Michael Ley (ley@uni-trier.de)