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BibTeX record conf/vlsid/SherigarMKD98
@inproceedings{DBLP:conf/vlsid/SherigarMKD98, author = {M. Bhaskar Sherigar and A. S. Mahadevan and K. Senthil Kumar and David S. Sumam}, title = {A Pipelined Parallel Processor to Implement {MD4} Message Digest Algorithm on Xilinx {FPGA}}, booktitle = {11th International Conference on {VLSI} Design {(VLSI} Design 1991), 4-7 January 1998, Chennai, India}, pages = {394--399}, publisher = {{IEEE} Computer Society}, year = {1998}, url = {https://doi.org/10.1109/ICVD.1998.646640}, doi = {10.1109/ICVD.1998.646640}, timestamp = {Fri, 24 Mar 2023 00:04:01 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/SherigarMKD98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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