<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/vlsid/SaxenaPL99" mdate="2005-03-02">
<author>Prashant Saxena</author>
<author>Peichen Pan</author>
<author>C. L. Liu</author>
<title>The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches.</title>
<pages>402-407</pages>
<year>1999</year>
<crossref>conf/vlsid/1999</crossref>
<booktitle>VLSI Design</booktitle>
<ee>http://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745189</ee>
<url>db/conf/vlsid/vlsid1999.html#SaxenaPL99</url>
</inproceedings>
</dblp>
