BibTeX record conf/vlsid/RajagopalSASVDCFSW06

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@inproceedings{DBLP:conf/vlsid/RajagopalSASVDCFSW06,
  author       = {K. A. Rajagopal and
                  R. Sivakumar and
                  N. V. Arvind and
                  C. Sreeram and
                  Vish Visvanathan and
                  Shailendra Dhuri and
                  Roopesh Chander and
                  Patrick Fortner and
                  Subra Sripada and
                  Qiuyang Wu},
  title        = {A Comprehensive Solution for True Hierarchical Timing and Crosstalk
                  Delay Signoff},
  booktitle    = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
                  3-7 January 2006, Hyderabad, India},
  pages        = {277--282},
  publisher    = {{IEEE} Computer Society},
  year         = {2006},
  url          = {https://doi.org/10.1109/VLSID.2006.8},
  doi          = {10.1109/VLSID.2006.8},
  timestamp    = {Fri, 24 Mar 2023 00:04:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/RajagopalSASVDCFSW06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}