Automatic Insertion of Gated Clocks at Register Transfer Level.

Nithya Raghavan Venkatesh Akella Smita Bakshi Automatic Insertion of Gated Clocks at Register Transfer Level. 48-54 1999 conf/vlsid/1999 VLSI Design http://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745123 db/conf/vlsid/vlsid1999.html#RaghavanAB99