BibTeX record conf/vlsid/RadeckaZ02

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@inproceedings{DBLP:conf/vlsid/RadeckaZ02,
  author       = {Katarzyna Radecka and
                  Zeljko Zilic},
  title        = {Identifying Redundant Wire Replacements for Synthesis and Verification},
  booktitle    = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
                  {(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
                  Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
  pages        = {517--523},
  publisher    = {{IEEE} Computer Society},
  year         = {2002},
  url          = {https://doi.org/10.1109/ASPDAC.2002.994972},
  doi          = {10.1109/ASPDAC.2002.994972},
  timestamp    = {Mon, 14 Nov 2022 15:28:09 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/RadeckaZ02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}