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BibTeX record conf/vlsid/PatilSBK13
@inproceedings{DBLP:conf/vlsid/PatilSBK13, author = {Vinay C. Patil and Sudarshan Srinivasan and Wayne P. Burleson and Sandip Kundu}, title = {Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis}, booktitle = {26th International Conference on {VLSI} Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013}, pages = {80--85}, publisher = {{IEEE} Computer Society}, year = {2013}, url = {https://doi.org/10.1109/VLSID.2013.167}, doi = {10.1109/VLSID.2013.167}, timestamp = {Fri, 24 Mar 2023 00:04:01 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/PatilSBK13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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