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@inproceedings{DBLP:conf/vlsid/ParekhjiVS93,
author = {Rubin A. Parekhji and
G. Venkatesh and
Sunil D. Sherlekar},
title = {State Assignment for Optimal Design of Monitored Self-Checking
Sequential Circuits},
booktitle = {VLSI Design},
year = {1993},
pages = {15-20},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
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