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@inproceedings{DBLP:conf/vlsid/KumarSJ93,
author = {P. R. Suresh Kumar and
Mandyam-Komar Srinivas and
James Jacob},
title = {Efficient Technique to Reduce Gate Evaluations and Speed
Up Fault Simulation},
booktitle = {VLSI Design},
year = {1993},
pages = {104},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
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