A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells.

Avaneendra Gupta John P. Hayes A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. 15-20 1997 conf/vlsid/1997 VLSI Design db/conf/vlsid/vlsid1997.html#GuptaH97