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BibTeX record conf/vlsid/GargCSK06
@inproceedings{DBLP:conf/vlsid/GargCSK06, author = {Vivek Garg and Vikram Chandrasekhar and Milagros Sashik{\'{a}}nth and V. Kamakoti}, title = {An Area and Configuration-Bit Optimized {CLB} Architecture and Timing-Driven Packing for FPGAs}, booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006), 3-7 January 2006, Hyderabad, India}, pages = {507--510}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/VLSID.2006.38}, doi = {10.1109/VLSID.2006.38}, timestamp = {Fri, 24 Mar 2023 00:04:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/GargCSK06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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