BibTeX record conf/vlsid/EnjapuriGSHT21

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@inproceedings{DBLP:conf/vlsid/EnjapuriGSHT21,
  author       = {Sriharsha Enjapuri and
                  Deepesh Gujjar and
                  Sandipan Sinha and
                  Ramesh Halli and
                  Manish Trivedi},
  title        = {A 5nm Wide Voltage Range Ultra High Density {SRAM} Design for {L2/L3}
                  Cache Applications},
  booktitle    = {34th International Conference on {VLSI} Design and 20th International
                  Conference on Embedded Systems, {VLSID} 2021, Guwahati, India, February
                  20-24, 2021},
  pages        = {151--156},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/VLSID51830.2021.00031},
  doi          = {10.1109/VLSID51830.2021.00031},
  timestamp    = {Mon, 14 Nov 2022 15:28:09 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/EnjapuriGSHT21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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