BibTeX record conf/vlsid/CortadellaYG02

• > Home > conf/vlsid/CortadellaYG02

@inproceedings{DBLP:conf/vlsid/CortadellaYG02,
  author       = {Jordi Cortadella and
                  Alexandre Yakovlev and
                  Jim D. Garside},
  title        = {Logic Design of Asynchronous Circuits (Tutorial Abstract)},
  booktitle    = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
                  {(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
                  Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
  pages        = {26},
  publisher    = {{IEEE} Computer Society},
  year         = {2002},
  url          = {https://doi.org/10.1109/ASPDAC.2002.994880},
  doi          = {10.1109/ASPDAC.2002.994880},
  timestamp    = {Mon, 14 Nov 2022 15:28:09 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/CortadellaYG02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}