Tutorial T3: Low Power Design Techniques for Nanometer Design Processes

Subhomoy Chattopadhyay Rakesh Patel Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. 5 2007 conf/vlsid/2007 VLSI Design http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.167 db/conf/vlsid/vlsid2007.html#ChattopadhyayP07