Francisco Barat Murali Jayapala Pieter Op de Beeck Geert Deconinck Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. 338-344 2002 conf/vlsid/2002 VLSI Design http://csdl.computer.org/comp/proceedings/vlsid/2002/1441/00/14410338abs.htm db/conf/vlsid/vlsid2002.html#BaratJBD02