Aditya Bansal Jae-Joon Kim Keunwoo Kim Saibal Mukhopadhyay Ching-Te Chuang Kaushik Roy Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. 125-130 2008 VLSI Design http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.50 conf/vlsid/2008 db/conf/vlsid/vlsid2008.html#BansalKKMCR08